It is known to use external oscillator circuits coupled to clock processing units such as microcontrollers or similar processing units. For example, in automotive applications, external quartz crystal oscillator circuits are used to clock microcontrollers that perform functions such as climate control and window lift control. In applications, such as automotive applications, networking, mobile phones, computing or similar applications, in which electrical circuits can be subjected to operating conditions which can cause disturbances, such as electromagnetic disturbances, the disturbances may produce unwanted signals or spikes on the clock signal which may cause logic to malfunction causing code runaway or application failures. Such failures can cause the application to crash with no further control other than resetting or restarting of the microcontroller which is undesirable.
Software techniques can be used to reduce the impact of spikes on the clock signal but these techniques require complex software routines and the spikes may cause the microcontroller to reach a state from which it cannot recover before the spikes can be removed.
A further challenge in improving the robustness of systems against clock disturbances arise in distributed systems, such as systems using CAN or FlexRay or similar protocols since in such systems the clock signal generated by the external oscillator circuit is used by different devices (e.g. the microcontroller and the peripheral devices) in the distributed system. Thus, any solution which attempts to remove or filter the clock disturbances is required to ensure that the phase shift to clock signal generated by the oscillator circuit is minimised for distributed systems.
In distributed system, a solution would be to use a Phase Lock Loop (PLL) circuit as the time base for the microcontroller and an external oscillator circuit as the time base for the peripheral devices in the distributed system. However, such a solution requires additional circuitry to handle the different time base domains and is not robust against clock disturbances on the external oscillator nor against disturbances of the microcontroller time base due to the PLL circuit itself.
Japanese patent application JP2006-005576 describes a clock filter circuit comprising two low pass filters which act as a delay and a RS flip-flop to remove unwanted signals from the clock signal. The circuit is arranged such that the filtered clock signal is not delayed with respect to the input clock. However, the circuit described in this patent application uses analog filters to act as delays and due to the variations of such analog filters over temperature and voltage such a circuit does not provide sufficient robustness for applications requiring enhanced protection against clock disturbances.
There is therefore a need to improve the robustness of systems against disturbances which produce unwanted signals on the clock signal.